Lesson Plan Duration : August 2018 to December 2018 |
Name of the Faculty : Ms. Shashee Lata Rajput |
Discipline : CSE |
Semester : 3rd |
Subject : Digital Electronics |
Lesson Plan Duration : August 2018 to December 2018 |
Week |
Theory |
Practical |
Lecture Day |
Topic |
Practical Day |
Topic |
1st |
1 |
Fundamentals Of Digital Systems And Logic Families: Digital signals, digital circuits |
1 |
Introduction to digital electronics lab- nomenclature of digital ICs, specifications, study of the datasheet, concept of Vcc and ground, verification of the truth tables of logic gates using TTL Ics |
2 |
AND, OR, NOT, NAND, NOR and Exclusive-OR operations |
3 |
Boolean algebra, examples of IC gates |
2nd |
4 |
Number systems-binary, signed binary |
2 |
Implementation of the given Boolean function using logic gates in both SOP and POS forms |
5 |
Octal hexadecimal number, binary arithmetic |
6 |
One’s and two’s complements arithmetic |
3rd |
7 |
Codes, error detecting and correcting codes |
3 |
Verification of state tables of RS, JK, T and D flip-flops using NAND & NOR gates |
8 |
Characteristics of digital lCs |
9 |
Digital logic families, TTL, Schottky TTL and CMOS logic |
4th |
10 |
Interfacing CMOS and TTL |
4 |
Implementation and verification of Decoder/De-multiplexer and Encoder using logic gates |
11 |
Tri-state logic. |
12 |
Combinational Digital Circuits : Standard representation for logic functions |
5th |
13 |
K-map representation |
5 |
Implementation of 4x1 multiplexer using logic gates |
14 |
Simplification of logic functions using K-map |
15 |
Minimization of logical functions |
6th |
16 |
Don’t care conditions, Multiplexer, De-Multiplexer/Decoders |
6 |
. Implementation of 4-bit parallel adder using 7483 IC |
17 |
Adders, Subtractors, BCD arithmetic |
18 |
Carry look ahead adder, serial adder |
7th |
19 |
ALU, elementary ALU design |
7 |
Design, and verify the 4-bit synchronous counter |
20 |
Popular MSI chips, digital comparator, parity checker/generator |
21 |
Code converters, priority encoders, decoders/drivers for display devices |
8th |
22 |
Q-M method of function realization |
8 |
Design, and verify the 4-bit asynchronous counter |
23 |
Sequential Circuits and Systems : A 1-bit memory, the circuit properties of Bistable latch |
24 |
The clocked SR flip flop, J- K-T and D types flip flops |
9th |
25 |
Applications of flip flops, shift registers, applications of shift registers |
9 |
Static and Dynamic Characteristic of NAND and Schmitt-NAND gate(both TTL and MOS) |
26 |
Serial to parallel converter, parallel to serial converter, ring counter |
27 |
Sequence generator, ripple (Asynchronous) counters, synchronous counters |
10th |
28 |
Counters design using flip flops, special counter IC’s |
10 |
Study of Arithmetic Logic Unit |
29 |
Asynchronous sequential counters, applications of counters |
30 |
A/D and D/A Converters : Digital to analog converters: weighted resistor/converter |
11th |
31 |
R-2R Ladder D/A converter, specifications for D/A converters, examples of D/A converter lCs |
11 |
Mini Project |
32 |
Sample and hold circuit, analog to digital converters: quantization and encoding |
33 |
Parallel comparator A/D converter, successive approximation A/D converter, counting A/D converter |
12th |
34 |
Dual slope A/D converter, A/D converter using voltage to frequency and voltage to time conversion, specifications of A/D converters, example of A/D converter Ics |
|
|
35 |
Semiconductor Memories and Programmable Logic Devices : Memory organization and operation, expanding memory size, classification and characteristics of memories |
36 |
Sequential memory, read only memory (ROM), read and write memory(RAM), content addressable memory (CAM), charge de coupled device memory (CCD) |
13th |
37 |
Commonly used memory chips, ROM as a PLD, Programmable logic array, Programmable array logic |
|
|
38 |
Complex Programmable logic devices (CPLDS), Field Programmable Gate Array (FPGA). |
39 |
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