Lesson Plan – Digital System Design

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Lesson Plan
Name of the Faculty          :   Ms. Shashi Lata
Discipline                            : ECE & CSE
Semester                            :  6th
Subject                               :   Digital System Design
Lesson Plan Duration     : Jan 2018 to April 2018
Week Theory Practical
Lecture Day Topic Practical Day Topic
1st 1 Computer-aided design tools for digital systems. Hardware description languages 1st Design all gates using VHDL.
2 identifiers, data objects
3 data types
2nd 4 data types 2nd Write VHDL programs for the followingcircuits,
check the waveforms and the hardware generated a.half adder b.full adder.
5 operators, logical operators
6 types of delays
3rd 7 types of delays contd 3rd Write VHDL programs for the followingcircuits,
check the waveforms and the hardware generated a.multiplexer b.demultiplexer.
8 entity
9 architecture declaration- dataflow modeling
4th 10 dataflow modeling contd. 4th Write VHDL programs for the followingcircuits,
check the waveforms and the hardware generated a.encoder b.decoder.
11 half adder, full adder
12 multiplexer, demultiplexer
5th 13 encoder, decoder 5th Write a VHDL program for a comparator and check the waveforms and the hardwaregenerated.
14 code converters
15 comparators,implementation of boolean algebra
6th 16 Revision session 6th Write a VHDL program for a code converter and check the waveforms and the hardwaregenerated.
17 sequential statements
18 sequential staements contd.
7th 19 process statement 7th Write a VHDL program for a FLIP FLOP and check the waveforms and the hardwaregenerated.
20 Process statement contd.
21 half adder, full adder
8th 22 multiplexer, demultiplexer 8th Write a VHDL program for a counter and check the waveforms and the hardwaregenerated.
23 encoder, decoder
24 code converters,comparator
9th 25 Revision session 9th Write VHDL programs for the following circuits, check the waveforms and the hardware generated a.register b. shift register.
26 Structural model- component declaration. Structural layout.
27 half adder, full adder
10th 28 multiplexer, demultiplexer 10th Implement any three (given above) on FPGA/CPLD kit.
29 encoder, decoder
30 code converters
11th 31 comparators
32 overloading
33 resolution functions
12th 34 resolution functions contd.
35 packages and libraries
36 subprograms- functions and procedure
13th 37 VHDL model & simulation of sequential circuits, shift registers, counters etc
38 generics
39 Basic components of computer, specifications
14th 40 Architecture and implementation of simple microcomputer system using VHDL
41 PLD: ROM, PLA, PAL, GAL
42 PEEL,CPLD, FPGA
15th 43 Design implementation using CPLD & FPGA